SSTUH32866 - 1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer

NXP Semiconductors

General Description

The SSTUH32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2 memory modules requiring a parity checking function.

It is deﬁned in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout.

Key Features

s Conﬁgurable register supporting DDR2 Registered DIMM.

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SSTUH32866 1.8 v high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer by NXP Semiconductors - Datasheet Preview

Datasheet Details

Part number	SSTUH32866
Manufacturer	NXP Semiconductors
File Size	186.62 KB
Description	1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
Datasheet	SSTUH32866 Datasheet

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Other Datasheets by NXP Semiconductors

Part Number	Description
SSTUH32864	1.8 V high output drive configurable registered buffer
SSTUH32865	1.8V 28-bit high output drive 1:2 registered buffer
SSTU32864	1.8V confgurable registered buffer
SSTU32865	28-bit 1:2 registered buffer
SSTU32866	1.8V 25-bit 1:1 or 14-bit 1:2 confgurable registered buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SSTUH32866 Rev. 01 — 13 May 2005 www.DataSheet4U.com 1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer with parity for DDR2 RDIMM applications Product data sheet 1. General description The SSTUH32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2 memory modules requiring a parity checking function. It is deﬁned in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout. The JEDEC standard for SSTUH32866 is pending publication. The register is conﬁgurable (using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter conﬁguration can be designated as Register A or Register B on the DIMM.