Datasheet4U Logo Datasheet4U.com

SSTU32866 - 1.8V 25-bit 1:1 or 14-bit 1:2 confgurable registered buffer

Description

The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function.

It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout.

Features

  • s s s s s s s s s s s s s s Configurable register supporting DDR2 Registered DIMM.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
SST108 N-Channel JFET Switch Calogic
SST108 Switching Micross
SST108 N-Channel JFETs Vishay
SST109 N-Channel JFET Switch Calogic
SST109 Switching Micross

Other Datasheets by NXP Semiconductors

Part Number Description
SSTU32864 1.8V confgurable registered buffer
SSTU32865 28-bit 1:2 registered buffer
SSTUA32864 configurable registered buffer
SSTUA32866 configurable registered buffer
SSTUB32866 configurable registered buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SSTU32866 Rev. 01 — 09 July 2004 www.DataSheet4U.com 1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications Objective data 1. Description The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending publication. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter configuration can be designated as Register A or Register B on the DIMM.
Published: |