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SSTUH32864 - 1.8 V high output drive configurable registered buffer

General Description

The SSTUH32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7 V to 1.9 V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

Key Features

  • s Configurable register supporting DDR2 Registered DIMM.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SSTUH32864 Rev. 01 — 22 April 2005 www.DataSheet4U.com 1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications Product data sheet 1. General description The SSTUH32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUH32864 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The C0 input controls the pinout configuration of the 1 : 2 pinout from A configuration (when LOW) to B configuration (when HIGH).