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Features
Two Cortex®-A55 processors operating up to 1.7 GHz.
32 KB L1 Instruction Cache.
32 KB L1 Data Cache.
64 KB per-core L2 cache.
Media Processing Engine (MPE) with Arm® NeonTM technology supporting the
Advanced Single Instruction Multiple Data architecture.
Floating Point Unit (FPU) with support of the Arm® VFPv4-D16 architecture
Support of 64-bit Arm® v8.2-A architecture
256 KB cluster L3 cache
Parity/ECC protection on L1 cache,.
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NXP Semiconductors Data Sheet: Technical Data Document Number: IMX93XEC Rev. 3, 12/2023 i.MX 93 Application Processors Data Sheet for Extended Industrial Products MIMX935...
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ication Processors Data Sheet for Extended Industrial Products MIMX9352XVVXMAB MIMX9332XVVXMAB MIMX9322XVXXMAB MIMX9312XVXXMAB MIMX9352XVTXMAB MIMX9332XVTXMAB MIMX9351XVVXMAB MIMX9331XVVXMAB MIMX9321XVXXMAB MIMX9311XVXXMAB MIMX9351XVTXMAB MIMX9331XVTXMAB Package Information Plastic Package FCBGA 11 x 11 mm, 0.5 mm pitch FCBGA 9 x 9 mm, 0.5 mm pitch FCBGA 14 x 14 mm, 0.65 mm pitch Ordering Information 1 i.MX 93 introduction See Table 2 on page 5 The i.MX 93 family represents NXP’s latest 1. i.MX 93 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MIMX9352XVVXMAB Datasheet
