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74LVC2G38 - Dual 2-input NAND gate

Description

The 74LVC2G38 provides a 2-input NAND function.

The outputs of the 74LVC2G38 devices are open-drain and can be connected to other open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions.

Inputs can be driven from either 3.3 V or 5 V devices.

Features

  • Wide supply voltage range from 1.65 V to 5.5 V.
  • 5 V tolerant outputs for interfacing with 5 V logic.
  • High noise immunity.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8B/JESD36 (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM EIA/JESD22-A114F exceeds 2000 V.
  • MM EIA/JESD22-A115-A exceeds 200 V.
  • 24 mA output drive (VCC = 3.0 V).
  • CMOS low power consumption.
  • Open-drain outputs.
  • Latch-up performa.

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Full PDF Text Transcription

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74LVC2G38 Dual 2-input NAND gate; open drain Rev. 11 — 8 April 2013 Product data sheet 1. General description The 74LVC2G38 provides a 2-input NAND function. The outputs of the 74LVC2G38 devices are open-drain and can be connected to other open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 1.65 V to 5.
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