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MPC93R51 - LOW VOLTAGE PLL CLOCK DRIVER

General Description

The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock.

Normal operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path.

Key Features

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More Datasheets from Motorola Semiconductor (now NXP Semiconductors)

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order Number: MPC93R51/D Rev 0, 12/2002 Low Voltage PLL Clock Driver The MPC93R51 is a 3.3V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 240 MHz and a maximum output skew of 150 ps the MPC93R51 is an ideal solution for the most demanding clock tree designs. The device offers 9 low skew clock outputs, each is configurable to support the clocking needs of the various high-performance microprocessors including the PowerQuicc II integrated communication microprocessor. The devices employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter. MPC93R51 LOW VOLTAGE 3.