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MPC931 - LOW VOLTAGE PLL CLOCK DRIVER

Download the MPC931 datasheet PDF. This datasheet also covers the MPC930 variant, as both devices belong to the same low voltage pll clock driver family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • for power conscious portable or “green” designs. The power down pin will seemlessly reduce all of the clock rates by one half so that the system will run at half the potential clock rate to extend battery life. The POWER_DN pin is synchronized internally to the slowest output clock rate. This allows the transition in and out of the power.
  • down mode to be output glitch free. In addition, the shut down control pins will turn off various combinations of clock outputs while leaving a subset a.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MPC930_Motorola.pdf) that lists specifications for multiple related part numbers.

More Datasheets from Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MPC9315 2.5V and 3.3V CMOS PLL Clock Generator/Driver
MPC930 LOW VOLTAGE PLL CLOCK DRIVER
MPC932 LOW VOLTAGE PLL CLOCK DRIVER
MPC9330 3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR
MPC9331 3.3 V 1:6 LVCMOS PLL Clock Generator
MPC9350 LOW VOLTAGE PLL CLOCK DRIVER
MPC9352 3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
MPC93R51 LOW VOLTAGE PLL CLOCK DRIVER
MPC93R52 LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR
MPC9100 DUAL PLL CLOCK GENERATOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC930/931 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock applications. With output frequencies of up to 150MHz and output skews of 300ps the MPC930/931 is ideal for the most demanding clock distribution designs. The device employs a fully differential PLL design to minimize cycle to cycle and long term jitter. This parameter is of significant importance when the clock driver is providing the reference clock for PLL’s on board todays microprocessors and ASiC’s. The device offers 6 low skew outputs, and a choice between internal or external feedback. The feedback option adds to the flexibility of the device, providing numerous input to output frequency relationships.