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IS61DDB44M18A - 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

General Description

The 72Mb IS61DDB42M36A and IS61DDB44M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 2Mx36 and 4Mx18 configuration available.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only.
  • Two input clocks (C and C#) for data ou.

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📁 Similar Datasheet

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IS61DDP2B21M36C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDB44M18 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB41M18A 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M36 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB41M36A 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB42M18 DDR-II (Burst of 4) CIO Synchronous SRAMs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61DDB44M18A IS61DDB42M36A 4Mx18, 2Mx36 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM JANUARY 2015 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two input clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to1.8V VDDQ, used with 0.75V to 0.9V VREF.  HSTL input and output interface.