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IS61DDB41M36A - 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

Download the IS61DDB41M36A datasheet PDF. This datasheet also covers the IS61DDB42M18A variant, as both devices belong to the same 36mb ddr-ii (burst 4) cio synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

1Mx36 and 2Mx18 configuration available.

window.

Common I/O read and write ports.

Synchronous pipeline read with late write operation.

write input ports.

Fixed 4-bit

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDB42M18A-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDB22M36C 72Mb DDR-II CIO SYNCHRONOUS SRAM ISSI
IS61DDB24M18C 72Mb DDR-II CIO SYNCHRONOUS SRAM ISSI
IS61DDP2B21M36C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDP2B21M36C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDP2B21M36C2 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDB41M36 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB41M18A 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB42M18 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M18A 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB42M36 DDR-II (Burst of 4) CIO Synchronous SRAMs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61DDB42M18A IS61DDB41M36A 2Mx18, 1Mx36 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM JANUARY 2015 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two input clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to1.8V VDDQ, used with 0.75V to 0.9V VREF.  HSTL input and output interface.