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IS61DDB44M18 - DDR-II (Burst of 4) CIO Synchronous SRAMs

General Description

The 72Mb IS61DDB42M36 and IS61DDB44M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 2M x 36 or 4M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with late write operation.
  • Double data rate (DDR-II) interface for read and write input ports.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges only.
  • Two input clocks (C an.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDB22M36C 72Mb DDR-II CIO SYNCHRONOUS SRAM ISSI
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IS61DDP2B21M36C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDP2B21M36C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDP2B21M36C2 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDB44M18A 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M18A 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M36 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB41M36A 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB42M18 DDR-II (Burst of 4) CIO Synchronous SRAMs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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I7D7D2DMR-bII (2M x 36 & 4M x (Burst o. f 4) CIO 18) Synchronous SRAMs A MAY 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation. • Double data rate (DDR-II) interface for read and write input ports. • Fixed 4-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two input clocks (C and C) for data output control. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.