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IDT71V546 - 128K x 36/ 3.3V Synchronous SRAM with ZBT Feature/ Burst Counter and Pipelined Outputs

Download the IDT71V546 datasheet PDF. This datasheet also covers the IDT-71V variant, as both devices belong to the same 128k x 36/ 3.3v synchronous sram with zbt feature/ burst counter and pipelined outputs family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Thus it has been given the name ZBTTM, or Zero Bus Turn-around.

Features

  • 128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized registered outputs eliminate the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT-71V-546.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71V546
Manufacturer Integrated Device Technology
File Size 178.20 KB
Description 128K x 36/ 3.3V Synchronous SRAM with ZBT Feature/ Burst Counter and Pipelined Outputs
Datasheet download datasheet IDT71V546 Datasheet

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Other Datasheets by Integrated Device Technology

Part Number Description
IDT71V509 128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBTO AND FLOW-THROUGH OUTPUT
IDT71V016SA 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)
IDT71V2546SA 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
IDT71V2548S 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
IDT71V2548SA 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs

Full PDF Text Transcription

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128K x 36, 3.3V Synchronous IDT71V546 SRAM with ZBT™ Feature, Burst Counter and Pipelined Outputs Features 128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized registered outputs eliminate the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability (interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion Single 3.
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