Datasheet4U Logo Datasheet4U.com

IS61QDPB41M36B2 - 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Download the IS61QDPB41M36B2 datasheet PDF (IS61QDPB42M18B included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 36mb quadp (burst 4) synchronous sram.

Description

1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interfa

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDPB42M18B-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • IS61C1024 - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C1024L - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C256 - 32K x 8 Low Voltage CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C25616 - 256K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C25616AL - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C25616AS - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C256AH - 32K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C256AL - 32K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C3216AL - 32K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)
  • IS61C512 - 64K x 8 High Speed CMOS Static RAM (Integrated Silicon Solution)
Other Datasheets by ISSI

Full PDF Text Transcription

Click to expand full text
IS61QDPB42M18B/B1/B2 IS61QDPB41M36B/B1/B2 2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.
Published: |