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IS61QDPB41M36B - 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Download the IS61QDPB41M36B datasheet PDF. This datasheet also covers the IS61QDPB42M18B variant, as both devices belong to the same 36mb quadp (burst 4) synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interfa

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDPB42M18B-ISSI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDPB41M36B1 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDPB41M36B2 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDPB41M36A 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDPB41M36A1 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDPB41M36A2 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Full PDF Text Transcription

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IS61QDPB42M18B/B1/B2 IS61QDPB41M36B/B1/B2 2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.
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