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IS61QDPB41M18A2 - 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Download the IS61QDPB41M18A2 datasheet PDF. This datasheet also covers the IS61QDPB41M18A variant, as both devices belong to the same 18mb quadp (burst 4) synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

512Kx36 and 1Mx18 configuration available.

valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) inter

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Note: The manufacturer provides a single datasheet file (IS61QDPB41M18A-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDPB41M18A 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDPB41M18A1 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDPB41M36A 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDPB41M36A1 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDPB41M36A2 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Full PDF Text Transcription

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IS61QDPB41M18A/A1/A2 IS61QDPB451236A/A1/A2 1Mx18, 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support. The 18Mb IS61QDPB451236A/A1/A2 and IS61QDPB41M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
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