IS61QDPB24M18A Datasheet PDF - ISSI 72Mb QUADP (Burst 2) Synchronous SRAM Specs

IS61QDPB24M18A - 72Mb QUADP (Burst 2) Synchronous SRAM

Datasheet Summary

Description

ODT option.

devices.

need for high-speed bus turnaround.

Features

2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and cont.

Datasheet Details

Part number	IS61QDPB24M18A
Manufacturer	ISSI
File Size	607.77 KB
Description	72Mb QUADP (Burst 2) Synchronous SRAM
Datasheet	IS61QDPB24M18A Datasheet
Additional preview pages of the IS61QDPB24M18A datasheet.

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Full PDF Text Transcription

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IS61QDPB24M18A/A1/A2 IS61QDPB22M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) AUGUST 2014 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data valid pin (QVLD).  +1.8V core power supply and 1.5, 1.

Published: Jun 10, 2016 |