IS61QDPB21M18A1 Datasheet PDF - ISSI 18Mb QUADP (Burst 2) Synchronous SRAM Specs

IS61QDPB21M18A1 - 18Mb QUADP (Burst 2) Synchronous SRAM

This page provides the datasheet information for the IS61QDPB21M18A1, a member of the IS61QDPB21M18A 18Mb QUADP (Burst 2) Synchronous SRAM family.

Datasheet Summary

Description

devices.

need for high-speed bus turnaround.

operations are self-timed.

Features

512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and co.

Datasheet Details

Part number	IS61QDPB21M18A1
Manufacturer	ISSI
File Size	600.50 KB
Description	18Mb QUADP (Burst 2) Synchronous SRAM
Datasheet	IS61QDPB21M18A1 Datasheet
Additional preview pages of the IS61QDPB21M18A1 datasheet.

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Full PDF Text Transcription

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IS61QDPB21M18A/A1/A2 IS61QDPB251236A/A1/A2 1Mx18, 512Kx36 18Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) OCTOBER 2014 FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.

Published: Jun 10, 2016 |