IS61QDPB24M18C Datasheet PDF - ISSI 72Mb QUADP Synchronous SRAM Specs

IS61QDPB24M18C - 72Mb QUADP Synchronous SRAM

Datasheet Summary

Description

at page 6 for each ODT option.

The IS61QDPB22M36C/C1/C2 and IS61QDPB24M18C/C1/ -C2 are 72Mb synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Max. 450 MHz clock for high bandwidth.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Two input clocks (K and K#) fo.

Datasheet Details

Part number	IS61QDPB24M18C
Manufacturer	ISSI
File Size	756.28 KB
Description	72Mb QUADP Synchronous SRAM
Datasheet	IS61QDPB24M18C Datasheet
Additional preview pages of the IS61QDPB24M18C datasheet.

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Full PDF Text Transcription

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IS61QDPB24M18C/C1/C2 IS61QDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Max. 450 MHz clock for high bandwidth  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data valid pin (QVLD).  +1.8V core power supply and 1.5, 1.

Published: Feb 18, 2024 |