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IS61LF25636 - (IS61LF25632 / IS61LF25636 / IS61LF51218) 256Kx32 Synchronous Flow-through Static RAM

Download the IS61LF25636 datasheet PDF. This datasheet also covers the IS61LF25632 variant, as both devices belong to the same (is61lf25632 / is61lf25636 / is61lf51218) 256kx32 synchronous flow-through static ram family and are provided as variant models within a single manufacturer datasheet.

Description

The ISSI IS61LF25632, IS61LF25636, and IS61LF51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance and memories for commucation and networking applications.

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • JEDEC 100-Pin TQFP and 119-pin PBGA package.
  • Power Supply + 3.3V VDD + 3.3V or 2.5V VDDQ (I/0).
  • Snooze MO.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61LF25632_ISSI.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IS61LF25636
Manufacturer ISSI (now Infineon)
File Size 220.51 KB
Description (IS61LF25632 / IS61LF25636 / IS61LF51218) 256Kx32 Synchronous Flow-through Static RAM
Datasheet download datasheet IS61LF25636 Datasheet

Full PDF Text Transcription

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( DataSheet : www.DataSheet4U.com ) IS61LF25632T/D/J IS61LF25636T/D/J IS61LF51218T/D/J 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP and 119-pin PBGA package • Power Supply + 3.3V VDD + 3.3V or 2.5V VDDQ (I/0) • Snooze MODE for reduced-power standby • T version (three chip selects) • J version (PBGA Package with JTAG) • D version (two chip selects) • JTAG Boundary Scan for PBGA.
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