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HY64UD16322M - 2M x 16 bit Low Low Power 1T/1C Pseudo SRAM

Description

- Power Up & Deep Power Down Exit Sequence Mar.

11.

‘ 02 Final Feb.

Features

  • CMOS Process Technology.
  • 2M x 16 bit Organization.
  • TTL compatible and Tri-state outputs.
  • Deep Power Down : Memory cell data hold invalid.
  • Standard pin configuration : 48-FBGA.
  • Data mask function by /LB, /UB.

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Datasheet Details

Part number HY64UD16322M
Manufacturer SK Hynix
File Size 283.27 KB
Description 2M x 16 bit Low Low Power 1T/1C Pseudo SRAM
Datasheet download datasheet HY64UD16322M Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.com HY64UD16322M Series Document Title 2M x 16 bit Low Low Power 1T/1C Pseudo SRAM Revision history Revision No. History 1.0 1.1 Initial Revised - Change Pin Connection - Improve tOE from 45ns to 30ns - Correct State Diagram 1.2 Revised - Correct Package Dimension - Change Absolute Maximum Ratings 1.3 Revised - DC Electrical Characteristics (ISB1,IDPD,ICC1) - State Diagram - Power Up Sequence - Deep Power Down Sequence - Read/Write Cycle Note - Release standby current from 100µA to 120µA 1.4 1.5 Revised - DC Electrical Characteristics (ICC1: 3mA -> 5mA) Revised - Add 70ns Part - Power Up Sequence 1.
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