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HY5S2B6DLF-BE - 4Banks x 2M x 16bits Synchronous DRAM

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDR Protocol Internal 4bank operation.
  • Voltage : VDD = 1.8V, VDDQ = 1.8V.
  • LVCMOS compatible I/O Interface.
  • Low Voltage interface to reduce I/O power.
  • Low Power Features - PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - Deep Power Down Mode.
  • Programmable CAS latency of 1, 2 or 3 Pakage Type : 54Ball FBGA - HY5S2B6DLF : Lead - HY5S2B6DLFP : Lead Free.

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Datasheet Details

Part number HY5S2B6DLF-BE
Manufacturer SK Hynix
File Size 791.81 KB
Description 4Banks x 2M x 16bits Synchronous DRAM
Datasheet download datasheet HY5S2B6DLF-BE Datasheet

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Full PDF Text Transcription

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HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 History Initial Draft Deleted Preliminary Changed Operation Voltage : 1.65(min) -> 1.70(min) Draft Date Dec. 2003 May. 2004 Feb. 2005 Remark Preliminary This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Feb. 2005 1 1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix Mobile SDR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
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