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HY5S5B2BLF-6E - 256M (8Mx32bit) Mobile SDRAM

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

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HY5S5B2BLFP-6E 256M (8Mx32bit) Mobile SDRAM
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Full PDF Text Transcription

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256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O Specification of 256M (8Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Apr. 2006 1 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2BLF(P) Series 11 Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. 0.1 Initial Draft 1. Changed 166MHz IDD1 : 85mA --> 90mA 133MHz IDD1 : 70mA --> 75mA 105MHz IDD1 : 50mA --> 60mA 2. Remove CL2 operation (Page 13 to 14) 1. Release History Draft Date Nov. 2005 Remark Preliminary 0.2 Mar. 2006 Preliminary 1.0 Apr. 2006 Final Rev 1.0 / Apr.
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