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H5DU5182ETR - (H5DU5162ETR / H5DU5182ETR) 512Mb DDR SDRAM

Download the H5DU5182ETR datasheet PDF. This datasheet also covers the H5DU5162ETR variant, as both devices belong to the same (h5du5162etr / h5du5182etr) 512mb ddr sdram family and are provided as variant models within a single manufacturer datasheet.

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL ali.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (H5DU5162ETR_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number H5DU5182ETR
Manufacturer SK Hynix
File Size 393.48 KB
Description (H5DU5162ETR / H5DU5182ETR) 512Mb DDR SDRAM
Datasheet download datasheet H5DU5182ETR Datasheet

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H5DU5162ETR (H5DU5162ETR / H5DU5182ETR) 512Mb DDR SDRAM
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Full PDF Text Transcription

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www.DataSheet4U.com 512Mb DDR SDRAM H5DU5182ETR H5DU5162ETR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Nov. 2009 1 www.DataSheet4U.com 1H5DU5182ETR H5DU5162ETR Revision History Revision No. 0.1 1.0 History Preliminary Release Draft Date Sep. 2009 Nov. 2009 Remark Rev. 1.0 / Nov. 2009 2 www.DataSheet4U.com 1H5DU5182ETR H5DU5162ETR DESCRIPTION The H5DU5182ETR and H5DU5162ETR are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
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