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BLD6G22LS-50 - W-CDMA 2110 MHz to 2170 MHz fully integrated Doherty transistor

Download the BLD6G22LS-50 datasheet PDF (BLD6G22L-50 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for w-cdma 2110 mhz to 2170 mhz fully integrated doherty transistor.

Description

The BLD6G22L-50 and BLD22LS-50 incorporate a fully integrated Doherty solution using Ampleon’s state of the art GEN6 LDMOS technology.

This device is perfectly suited for CDMA base station applications at frequencies from 2110 MHz to 2170 MHz.

Features

  • Typical W-CDMA performance at frequencies from 2110 MHz to 2170 MHz:.
  • Average output power = 8 W.
  • Power gain = 14 dB.
  • Efficiency = 40 %.
  • Fully optimized integrated Doherty concept:.
  • integrated asymmetrical power splitter at input.
  • integrated power combiner.
  • peak biasing down to 0 V.
  • low junction temperature.
  • high efficiency BLD6G22L-50; BLD6G22LS-50 W-CDMA 2110 MHz to 2170 MHz fully integrated Doherty transistor.
  • 100 % peak power tested f.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (BLD6G22L-50-Ampleon.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number BLD6G22LS-50
Manufacturer Ampleon
File Size 0.98 MB
Description W-CDMA 2110 MHz to 2170 MHz fully integrated Doherty transistor
Datasheet download datasheet BLD6G22LS-50 Datasheet

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Full PDF Text Transcription

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BLD6G22L-50; BLD6G22LS-50 W-CDMA 2110 MHz to 2170 MHz fully integrated Doherty transistor Rev. 4 — 1 September 2015 Product data sheet 1. Product profile 1.1 General description The BLD6G22L-50 and BLD22LS-50 incorporate a fully integrated Doherty solution using Ampleon’s state of the art GEN6 LDMOS technology. This device is perfectly suited for CDMA base station applications at frequencies from 2110 MHz to 2170 MHz. The main and peak device, input splitter and output combiner are integrated in a single package. This package consists of one gate and drain lead and two extra leads of which one is used for biasing the peak amplifier and the other is not connected. It only requires the proper input/output match and bias setting as with a normal class-AB transistor. Table 1.
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