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OR3TP12 - Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Description

7 What Is an FPSC?

Features

  • include registers for device and subsystem identification and autoconfiguration, support for 64-bit addressing, and multimaster capability that allows any PCI bus Master access to any PCI bus Target. PCI Bus Core Highlights s Implemented in an ORCA Series 3 base array, displacing the bottom four rows of 18 columns. Core is a well-tested ASIC model. Fully compliant to Revision 2.1 of PCI Local Bus Specification (and designed for Revision 2.2). s s.
  • PCI Local Bus Specification Rev. 2.1, P.

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Datasheet Details

Part number OR3TP12
Manufacturer Agere Systems
File Size 2.39 MB
Description Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
Datasheet download datasheet OR3TP12 Datasheet
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Full PDF Text Transcription

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Data Sheet March 2000 ORCA® OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface Introduction Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of an FPGA-based design implementation coupled with the high bandwidth of the industry-standard PCI interface. The ORCA OR3TP12 FPSC provides a full-featured 33/50/66 MHz, 32-/64-bit PCI interface, fully designed and tested, in hardware, plus FPGA logic for user-programmable functions. Table 1.
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