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74HC107D - Dual JK flip-flop

Download the 74HC107D datasheet PDF. This datasheet also covers the 74HC107 variant, as both devices belong to the same dual jk flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs.

The reset is an asynchronous active LOW input and operates independently of the clock input.

Key Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Input levels:.
  • The 74HC107: CMOS levels.
  • The 74HCT107: TTL levels.
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
  • CD.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC107-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74HC107 Dual JK flip-flop Philips
74HC10 Triple 3-input NAND gate Philips
74HC10 Triple 3-Input NAND Gates Texas Instruments
74HC109 Dual J-K Positive-Edge-Triggered Flip-Flops Texas Instruments
74HC109 Dual JK flip-flop Philips

Other Datasheets by Nexperia

Part Number Description
74HC107 Dual JK flip-flop
74HC107-Q100 Dual JK flip-flop
74HC10 Triple 3-input NAND gate
74HC10-Q100 Triple 3-input NAND gate
74HC109 Dual JK flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev. 7 — 20 February 2024 Product data sheet 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.