74HC10
FEATURES
- Output capability: standard
- ICC category: SSI GENERAL DESCRIPTION
74HC/HCT10
The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL/ t PLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × f O) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in p F VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC
- 1.5 V. ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PARAMETER propagation delay n A, n B, n C to n Y input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V...
