74HC107
FEATURES
- Output capability: standard
- ICC category: flip-flops GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A.
74HC/HCT107
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (n CP) and reset (n R) inputs; also plementary Q and Q outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (n R) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay n CP to n Q n CP to n Q n R to n Q, n Q fmax CI CPD Notes 1. CPD is used to...
