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SN74SSQEB32882 28-Bit to 56-Bit Registered Buffer

SN74SSQEB32882 Description

SN74SSQEB32882 www.ti.com SCAS896-PUB * JUNE 2010 28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differen.
This JEDEC SSTE32882 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs wi.

SN74SSQEB32882 Features

* 1
* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs
* CKE Powerdown Mode for Optimized System Power Consumption
* 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Dif

SN74SSQEB32882 Applications

* DDR3 Registered DIMMs up to DDR3-1866
* DDR3L Registered DIMMs up to DDR3L-1600
* DDR3U Registered DIMMs up to DDR3U-1333

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28-Bit 56-Bit Registered Buffer Texas Instruments
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