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DS92LV18 - 18-Bit Bus LVDS Serializer/Deserializer

Description

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18

bit parallel bus into a BLVDS serial stream with embedded clock information.

Features

  • 1.
  • 2 15.
  • 66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput).
  • Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins.
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data).
  • Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks.
  • Line and Local Loopback Modes.
  • Robust BLVDS Serial Transm.

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📁 Similar Datasheet

Part Number Description Manufacturer
DS92LV18 18-Bit Bus LVDS Serializer/Deserializer National Semiconductor
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DS92LV1023 40-66 MHz 10 Bit Bus LVDS Serializer/Deserializer National Semiconductor
DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer National Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
DS92LV1021 LVDS Serializer/Deserializer
DS92LV1210 LVDS Serializer/Deserializer
DS92LV1260 Six Channel 10 Bit BLVDS Deserializer
DS92LV16 16-Bit Bus LVDS Serializer/Deserializer
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver

Full PDF Text Transcription

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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz Check for Samples: DS92LV18 FEATURES 1 •2 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput) • Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data) • Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks • Line and Local Loopback Modes • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI • No External Coding Required • Internal PLL, No External PLL Components Required • Single +3.
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