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CDCLVD2106 - Dual 1:6 Low Additive Jitter LVDS Buffer

Description

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11).

Each buffer block consists of one input and 6 LVDS outputs.

The inputs can either be LVDS, LVPECL, or LVCMOS.

Features

  • 1.
  • Dual 1:6 Differential Buffer.
  • Low Additive Jitter:.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2106 FEATURES 1 • Dual 1:6 Differential Buffer • Low Additive Jitter: <300 fs rms in 10 kHz – 20 MHz • Low Within Bank Output Skew of 45 ps (Max) • Universal Inputs Accept LVDS, LVPECL, LVCMOS • One Input Dedicated for Six Outputs • Total of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible • Clock Frequency up to 800 MHz • 2.375–2.
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