Datasheet4U Logo Datasheet4U.com

74HC109 - Dual J-K Positive-Edge-Triggered Flip-Flops

Datasheet Summary

Description

These devices contain two independent J-K positiveedge-triggered flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.

Features

  • Wide operating voltage range of 2 V to 6 V.
  • Low input current of 1 μA max.
  • High-current outputs drive up to 10 LSTTL loads.
  • Low power consumption, 40-μA max ICC.
  • Typical tpd = 12 ns.
  • ±4-mA output drive at 5 V 2.

📥 Download Datasheet

Datasheet preview – 74HC109

Datasheet Details

Part number 74HC109
Manufacturer Texas Instruments
File Size 1.67 MB
Description Dual J-K Positive-Edge-Triggered Flip-Flops
Datasheet download datasheet 74HC109 Datasheet
Additional preview pages of the 74HC109 datasheet.

📁 Similar Datasheet

  • 74HC109 - Dual JK flip-flop (nexperia)
  • 74HC109 - Dual JK flip-flop (Philips)
  • 74HC109-Q100 - Dual JK flip-flop (nexperia)
  • 74HC109D - Dual JK flip-flop (nexperia)
  • 74HC10 - Triple 3-input NAND gate (Philips)
  • 74HC10 - Triple 3-input NAND gate (nexperia)
  • 74HC10-Q100 - Triple 3-input NAND gate (nexperia)
  • 74HC107 - Dual JK flip-flop (Philips)
  • 74HC107 - Dual JK flip-flop (nexperia)
  • 74HC107-Q100 - Dual JK flip-flop (nexperia)
Other Datasheets by Texas Instruments
  • 74HC10 - Triple 3-Input NAND Gates
  • 74HC11 - Triple 3-Input AND Gate
  • 74HC112 - Dual J-K Negative-Edge-Triggered Flip-Flops
  • 74HC123 - High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators
  • 74HC125 - Quadruple Buffers
  • 74HC132 - Quadruple 2-Input NAND Gates
  • 74HC137 - High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer
  • 74HC138 - 3-Line To 8-Line Decoders/Demultiplexers

Full PDF Text Transcription

Click to expand full text
SN54HC109, SN74HC109 SCLS470C – MARCH 2003 – REVISED JUNE 2022 SNx4HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 1 Features • Wide operating voltage range of 2 V to 6 V • Low input current of 1 μA max • High-current outputs drive up to 10 LSTTL loads • Low power consumption, 40-μA max ICC • Typical tpd = 12 ns • ±4-mA output drive at 5 V 2 Description These devices contain two independent J-K positiveedge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse.
Published: |