XC5200 - Field Programmable Gate Arrays

Xilinx

Datasheet Details

Part number	XC5200
Manufacturer	Xilinx
File Size	568.70 KB
Description	Field Programmable Gate Arrays
Datasheet	XC5200-Xilinx.pdf

Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”) - Price competitive with Gate Arrays.
System Level Features - System performance beyond 50 MHz - 6 levels of interconnect hierarchy - VersaRing™ I/O Interface for pin-locking - Dedicated carry logic for high-speed arithmetic functions - Cascade chain for wide input functions - Built-in IEEE 1149.1 JTAG bound.

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Published: Dec 17, 2017 |