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LH543611 - 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO

Description

The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2.

These operate in parallel, but in opposite directions, for bidirectional data buffering.

FIFO #1 and FIFO #2 each are organized as 512 or 1024 by 36 bits.

Features

  • Pin-Compatible and Functionally.
  • Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper Expanded Control Register that is Fully Readable as well as Writeable Fast Cycle Times: 18/20/25/30/35 ns Improved Input Setup and Flag Out Timing.

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Datasheet preview – LH543611

Datasheet Details

Part number LH543611
Manufacturer Sharp Corporation
File Size 475.96 KB
Description 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO
Datasheet download datasheet LH543611 Datasheet
Additional preview pages of the LH543611 datasheet.

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Other Datasheets by Sharp Electrionic Components
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Full PDF Text Transcription

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LH543611/21 FEATURES • Pin-Compatible and Functionally • • • • • • • • • • • • • • • • • • • • • • • • • Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper Expanded Control Register that is Fully Readable as well as Writeable Fast Cycle Times: 18/20/25/30/35 ns Improved Input Setup and Flag Out Timing Two 512 × 36-bit FIFO Buffers (LH543611) or Two 1024 × 36-bit FIFO Buffers (LH543621) Full 36-bit Word Width Selectable 36/18/9-bit Word Width on Port B; Selection May be Changed Without Resetting the BiFIFO Programmable Byte-Order Reversal – ‘Big-Endian ↔ Little-Endian Conversion’ Independently-Synchronized (‘Fully-Asynchronous’) Operation of Port A and Port B ‘Synchronous’ Enable-Plus-Clock Control at Both Ports R/W, Enable, Request, and Address Control Inputs are Sampled on the
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