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LH540202 - CMOS 1024 x 9 Asynchronous FIFO

General Description

The LH540202 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 1024 nine-bit words.

It follows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs.

Key Features

  • Fast Access Times: 15/20/25/35/50 ns.
  • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology.
  • Input Port and Output Port Have Entirely Independent Timing.
  • Expandable in Width and Depth.
  • Full, Half-Full, and Empty Status Flags.
  • Data Retransmission Capability.
  • TTL-Compatible I/O.
  • Pin and Functionally Compatible with Sharp LH5497 and with Am/IDT/MS7202.
  • Industrial Temperature Grade Option Currentl.

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Other Datasheets by Sharp Corporation

Part Number Description
LH540203 CMOS 2048 x 9 Asynchronous FIFO
LH540204 CMOS 4096 x 9 Asynchronous FIFO
LH540205 CMOS 8192 x 9 Asynchronous FIFO
LH540215 512 x 18 / 1024 x 18 Synchronous FIFO
LH540225 512 x 18 / 1024 x 18 Synchronous FIFO

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LH540202 FEATURES • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags • Data Retransmission Capability • TTL-Compatible I/O • Pin and Functionally Compatible with Sharp LH5497 and with Am/IDT/MS7202 • Industrial Temperature Grade Option Currently Available With Sharp LH5497H only (Contact a Sharp Representative for More Information) • Control Signals Assertive-LOW for Noise Immunity • Packages: 28-Pin, 300-mil PDIP 28-Pin, 300-mil SOJ * 32-Pin PLCC CMOS 1024 × 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION The LH540202 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dua