Description
www.DataSheet4U.com K4Y5416(/08/04)4UF XDR DRAM 256Mbit XDR DRAM(F-die) 2M x 16(/8/4) bit x 8s Banks Version 1.0 Jan.2005 Version 1.0 Jan.2005 .
XDR DRAM
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions.
Features
* Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling
* Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count
* Programmable on-chip termination - Adaptive impedance matching - Reduced system cost
Applications
* including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 256Mb XDR DRAM device is a CMOS DRAM organized as 16M words by 16bits. The use of Differential Rambus Signaling Level(DRSL) technology permits 4000/3200/2400 Mb/s transfer ra
