K4H560838D-TCB3 - 256Mb D-die DDR Sdram

Samsung Semiconductor

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Datasheet Details

Part number	K4H560838D-TCB3
Manufacturer	Samsung Semiconductor
File Size	205.14 KB
Description	256Mb D-die DDR Sdram
Datasheet	K4H560838D-TCB3_SamsungSemiconductor.pdf

K4H560838D-TCB3 Product details

Description

SYMBOL CK, CK DDR SDRAM TYPE Input DESCRIPTION Clock : CK and CK are differential clock inputs.All address and control input signals are sampled on the positive edge of CK and negative edge of CK.Output (read) data is referenced to both edges of CK.Internal clock signals are derived from CK/CK.Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers.Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH

Features

Double-data-rate architecture; two data transfers per clock cycle.
Bidirectional data strobe(DQS).
Four banks operation.
Differential clock inputs(CK and CK).
DLL aligns DQ and DQS transition with CK transition.
MRS cycle with address key programs -. Read latency 2, 2.5 (clock) www. DataSheet4U. com -. Burst length (2, 4, 8) -. Burst type (sequential & interleave).
All inputs except data & DM are sampled at the positive going edge of.

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Published: Aug 13, 2008 |