NBSG16MMNR2 - 2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

NBSG16MMNR2 Datasheet Preview — Preview of NBSG16MMNR2 PDF

Datasheet Details

Part number	NBSG16MMNR2
Manufacturer	ON
File Size	81.31 KB
Description	2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
Datasheet	NBSG16MMNR2_ONSemiconductor.pdf

NBSG16MMNR2 Product details

Description

I/O LVDS, CML, ECL, LVTTL, LVCMOS Input LVDS, CML, ECL, LVTTL, LVCMOS Input CML Output CML Output ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Description Internal 50 W Termination Pin.See Table 2. (Note 3) Inverted Differential Input (Note 3) Noninverted Differential Input.(Note 3) Internal 50 W Termination Pin.See Table 2. (Note 3) Positive Supply Voltage.A

Features

urrent (@ VIL) VEE + 1.275 VEE 1875 1.2 Min 37 VCC.
40 Typ 43 VCC.
10 VCC.
400 VCC.
1.0.
VCC.
1.4.
1970 Max 51 VCC VCC.
330 VCC VIH.
0.150 2065 3.3 VEE + 1.275 VEE 1875 1.2 Min 37 VCC.
40 25°C Typ 43 VCC.
10 VCC.
400 VCC.
1.0.
VCC.
1.4.
1970 Max 51 VCC VCC.
330 VCC VIH.
0.150 2065 3.3 VEE + 1.275 VEE 1875 1.2 Min 37 VCC.
40 85°C Typ 43 VCC.

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Published: May 12, 2005 |