NBSG53A - 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider

Product Overview

ON Semiconductor

Part number	NBSG53A
Manufacturer	ON Semiconductor
File Size	162.14 KB
Description	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider
Datasheet	NBSG53A Datasheet
Additional preview pages of the NBSG53A datasheet.

Pin Name I/O Description 1 VTCLK Internal 50 W Termination Pin. Internal 50 W Termination Pin. Internal 50 W termination pin.

Maximum Input Clock Frequency (DFF) > 8 GHz Typical (See Figures 3, 5, 7, 9, and 10).
Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical (See Figures 4, 6, 8, 9, and 10).
210 ps Typical Propagation Delay (OLS = FLOAT).
45 ps Typical Rise and Fall Times (OLS = FLOAT).
DIV/2 Mode (Active with Select Low).
DFF Mode (Active with Select High).
Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V.

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Published: Apr 24, 2007 |