SN74LS109 Datasheet (ON Semiconductor)

SN74LS109, LOW POWER SCHOTTKY

SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops.

The clocking operation is independent of rise and fall times of the clock waveform.

The JK design allows operation as a D flip-flop by simply connecting the J and K pins together.

http://onsemi.com MODE SELECT TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) L H