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NB4N11S 3.3V 1:2 AnyLevel Input to LVDS Fanout Buffer /Translator

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Description

NB4N11S 3.3 V 1:2 AnyLevelâ„¢ Input to LVDS Fanout Buffer / Translator The NB4N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EP Name Q0 Q0 Q1 Q1 VCC NC VEE VEE VTD D D VTD VCC VCC VCC VCC. LVPECL, CML, LVDS, LVCMOS, LVTTL L.

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Features

* www. DataSheet4U. com http://onsemi. com MARKING DIAGRAM
* 16 1 1 QFN
* 16 MN SUFFIX CASE 485G NB4N 11S ALYW A L Y W = Assembly Location = Wafer Lot = Year = Work Week
* Maximum Input Clock Frequency > 2.0 GHz Maximum

Applications

* The NB4N11S has a wide input common mode range from GND + 50 mV to VCC
* 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB4N11S is ideal for translating a variety of differential or single
* ended Clock or Data signals to 350 mV typical LVDS output lev

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