DS99R103 - (DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer

Product Overview

National Semiconductor

Part number	DS99R103
Manufacturer	National Semiconductor
File Size	913.87 KB
Description	(DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer
Datasheet	DS99R103 Datasheet
Additional preview pages of the DS99R103 datasheet.

The DS99R103/104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

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3 MHz.
40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions.
Capable to drive shielded twisted-pair cable.
User selectable clock edge for parallel data on both Transmitter and Receiver coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed All codes RDL (random da.

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Published: Jul 21, 2007 |