DS90CF363 Datasheet (National Semiconductor)

DS90CF363, +3.3V LVDS Transmitter

The DS90CF363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.

Every cycle of the transmit clock 21 bits of input data are sampled a

DS90CF363 Features

* n n n n n n n n n n n n n n n n 20 to 65 MHz shift clock support Single 3.3V supply Chipset (Tx + Rx) power consumption < 250 mW (typ) Power-down mode ( < 0.5 mW total) Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and higher addressability. Up to 170 Megabytes/sec bandwidth Up