Datasheet Details
| Part number | DM74LS256 |
|---|---|
| Manufacturer | National Semiconductor |
| File Size | 127.06 KB |
| Description | Dual 4-Bit Addressable Latch |
| Datasheet |
 DM74LS256 Datasheet
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| Part number | DM74LS256 |
|---|---|
| Manufacturer | National Semiconductor |
| File Size | 127.06 KB |
| Description | Dual 4-Bit Addressable Latch |
| Datasheet |
DM74LS256 Datasheet
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The ’LS256 is a dual 4-bit addressable latch with common control inputs these include two Address inputs (A0 A1) an active LOW enable input (E) and an active LOW Clear input (CL) Each latch has a Data input (D) and four outputs (Q0 Q3) When the Enable (E) is HIGH and the Clear input (CL) is LOW all outputs (Q0 Q3) are LOW Dual 4-channel demultiplexing occurs when the CL and E are both LOW When CL is HIGH and E is LOW the selected output (Q0 Q3) determined by the Addre
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