Datasheet4U Logo Datasheet4U.com

74AUP2G17 Low-power dual Schmitt trigger

74AUP2G17 Description

www.DataSheet4U.com 74AUP2G17 Low-power dual Schmitt trigger Rev.02 * 10 January 2008 Product data sheet 1.General .
The 74AUP2G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74AUP2G17 Features

* s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E Class 3A exceeds 5000

74AUP2G17 Applications

* using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The

📥 Download Datasheet

Preview of 74AUP2G17 PDF
datasheet Preview Page 2 datasheet Preview Page 3

📁 Related Datasheet

  • 74AUP2G125 - DUAL 3-STATE BUFFER (Diodes)
  • 74AUP2G126 - DUAL 3-STATE BUFFER (Diodes)
  • 74AUP2G132 - Low-power dual 2-input NAND Schmitt trigger (nexperia)
  • 74AUP2G14 - DUAL SCHMITT TRIGGER INVERTERS (Diodes)
  • 74AUP2G157 - Low-power 2-input multiplexer (nexperia)
  • 74AUP2G16 - Low-power dual buffer (nexperia)
  • 74AUP2G00 - Low-power dual 2-input NAND gate (NXP)
  • 74AUP2G00-Q100 - Low-power dual 2-input NAND gate (nexperia)

📌 All Tags

Low-power dual Schmitt trigger NXP Semiconductors
NXP Semiconductors 74AUP2G17-like datasheet