S7A401830M Description
SSSS7777AAAA444400001331866833330000MMMM 128Kx36 & 256Kx18 Sync-Pipelined Burst SRAM 128Kx36 & 256Kx18 Sync-Pipelined Burst SRAM 4Mb Sync.Pipelined.
The S7A403630M and S7A401830M are 4,718,592-bit Synchronous Static Random Access Memory designed for high performance.
S7A401830M Features
* VDD = 2.5V(2.3V ~ 2.7V) or 3.3V(3.1V ~ 3.5V) Power Supply
* VDDQ = 2.3V~2.7V I/O Power Supply (VDD=2.5V) or
2.3V~3.5V I/O Power Supply (VDD=3.3V)
* Synchronous Operation
* 2 Stage Pipelined operation with 4 Burst
* On-Chip Address Counter
* Self-Time
S7A401830M Applications
* GW, BW, LBO, ZZ. Write cycles are internally selftimed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address
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