74LS174 Datasheet (Motorola)

74LS174, HEX D FLIP-FLOP

The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs.

The Clock (CP) and Master Reset (MR) are common to all flip-flops.

Each D input’s state is transferred to the corresponding flipflop’s output following the LOW to HIGH Clock (CP) transition.

A LOW input to

SN54/74LS174 HEX D FLIP-FLOP The LSTTL / MSI SN54 / 74LS174 is a high speed Hex D Flip-Flop.

The device is used primarily as a 6-bit edge-triggered storage register.

The information on the D inputs is transferred to storage during the LOW to HIGH clock transition.

The device has a Master Reset to simultaneously clear all flip-flops.

The LS174 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.

HEX D FLIP-FLOP LOW POWE