Datasheet Details
| Part number | 74LS107 |
|---|---|
| Manufacturer | ETC |
| File Size | 143.69 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
| Datasheet |
 74LS107_ETC.pdf
|
| Part number | 74LS107 |
|---|---|
| Manufacturer | ETC |
| File Size | 143.69 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
| Datasheet |
74LS107_ETC.pdf
|
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse The data on the J and K inputs may change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated A low logic le
📁 74LS107 Similar Datasheet