MT4LC4M4B1 - DRAM

Product Overview

Micron Technology

Part number	MT4LC4M4B1
Manufacturer	Micron Technology
File Size	360.24 KB
Description	DRAM
Datasheet	MT4LC4M4B1 Datasheet
Additional preview pages of the MT4LC4M4B1 datasheet.

The 4 Meg x 4 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x4 configuration.

Industry-standard x4 pinout, timing, functions, and packages.
High-performance, low-power CMOS silicon-gate process.
Single power supply (+3.3V ±0.3V or +5V ±0.5V).
All inputs, outputs and clocks are TTL-compatible.
Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR).
Optional self refresh (S) for low-power data retention.
11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh).
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Published: Jan 16, 2006 |