MT4LC4M16F5 Datasheet (Micron Technology)

MT4LC4M16F5, DRAM

The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits organized in a x16 configuration.

The MT4LC4M16F5 is functionally organized as 4,194,304 locations containing 16 bits each.

The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 colu

MT4LC4M16F5 Features

* Single +3.3V ±0.3V power supply

* Industry-standard x16 pinout, timing, functions, and packages

* 12 row, 10 column addresses

* High-performance CMOS silicon-gate process

* All inputs, outputs and clocks are LVTTL-compatible

* FAST PAGE MODE (FPM) ac