IDTCV107E - CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

Integrated Device Technology

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Datasheet Details

Part number	IDTCV107E
Manufacturer	Integrated Device Technology
File Size	215.39 KB
Description	CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
Datasheet	IDTCV107E_IntegratedDeviceTechnology.pdf

IDTCV107E Product details

Description

KEY SPECIFICATION: CPU/SRC CLK cycle to cycle jitter < 125ps SATA CLK cycle to cycle jitter < 125ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error as low as 36 ppm FUNCTIONAL BLOCK DIAGRAM DataSheet4U.com PLL1 SSC EasyN Programming CPU CLK Output Buffers CPU[1:0] DataShee X1 XTAL Osc Amp IREF REF 2.1.0 X2 PLL2 SSC EasyN Programming SDATA SCLK SM Bus Controller AGP/PCI Output Buffers PCI[5:0], PCIF[2:0] 3V66[3:0] PLL3 SS

Features

4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz CPU frequency VCO frequency up to 1.1G Support index block read/write, single cycle index block read Programmable REF, 3V66, PCI, 48MHz I/O drive strength Programmable 3V66 and PCI Skew Available in S.

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Published: Oct 11, 2006 |